Wafer-Level Testing and Test During Burn-In for Integrated Circuits
Sudarshan Bahukudumbi, Krishnendu Chakrabarty
ISBN: | 9781596939905 |
Publisher: | Artech House |
Published: | 1 February, 2010 |
Format: | ePub |
Editions: |
1 other edition
of this product
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Wafer-Level Testing and Test During Burn-In for Integrated Circuits
Sudarshan Bahukudumbi, Krishnendu Chakrabarty
Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This hands-on resource provides a comprehensive analysis of these methods, showing how wafer-level testing during burn-in (WLTBI) helps lower product cost in semiconductor manufacturing. Engineers learn h
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